
grayscale-processing:     file format elf64-littleaarch64


Disassembly of section .init:

0000000000400608 <_init>:
  400608:	a9bf7bfd 	stp	x29, x30, [sp, #-16]!
  40060c:	910003fd 	mov	x29, sp
  400610:	94000046 	bl	400728 <call_weak_fn>
  400614:	a8c17bfd 	ldp	x29, x30, [sp], #16
  400618:	d65f03c0 	ret

Disassembly of section .plt:

0000000000400620 <.plt>:
  400620:	a9bf7bf0 	stp	x16, x30, [sp, #-16]!
  400624:	b0000090 	adrp	x16, 411000 <__FRAME_END__+0x10084>
  400628:	f947fe11 	ldr	x17, [x16, #4088]
  40062c:	913fe210 	add	x16, x16, #0xff8
  400630:	d61f0220 	br	x17
  400634:	d503201f 	nop
  400638:	d503201f 	nop
  40063c:	d503201f 	nop

0000000000400640 <perror@plt>:
  400640:	d0000090 	adrp	x16, 412000 <perror@GLIBC_2.17>
  400644:	f9400211 	ldr	x17, [x16]
  400648:	91000210 	add	x16, x16, #0x0
  40064c:	d61f0220 	br	x17

0000000000400650 <atoi@plt>:
  400650:	d0000090 	adrp	x16, 412000 <perror@GLIBC_2.17>
  400654:	f9400611 	ldr	x17, [x16, #8]
  400658:	91002210 	add	x16, x16, #0x8
  40065c:	d61f0220 	br	x17

0000000000400660 <open@plt>:
  400660:	d0000090 	adrp	x16, 412000 <perror@GLIBC_2.17>
  400664:	f9400a11 	ldr	x17, [x16, #16]
  400668:	91004210 	add	x16, x16, #0x10
  40066c:	d61f0220 	br	x17

0000000000400670 <__libc_start_main@plt>:
  400670:	d0000090 	adrp	x16, 412000 <perror@GLIBC_2.17>
  400674:	f9400e11 	ldr	x17, [x16, #24]
  400678:	91006210 	add	x16, x16, #0x18
  40067c:	d61f0220 	br	x17

0000000000400680 <close@plt>:
  400680:	d0000090 	adrp	x16, 412000 <perror@GLIBC_2.17>
  400684:	f9401211 	ldr	x17, [x16, #32]
  400688:	91008210 	add	x16, x16, #0x20
  40068c:	d61f0220 	br	x17

0000000000400690 <__gmon_start__@plt>:
  400690:	d0000090 	adrp	x16, 412000 <perror@GLIBC_2.17>
  400694:	f9401611 	ldr	x17, [x16, #40]
  400698:	9100a210 	add	x16, x16, #0x28
  40069c:	d61f0220 	br	x17

00000000004006a0 <write@plt>:
  4006a0:	d0000090 	adrp	x16, 412000 <perror@GLIBC_2.17>
  4006a4:	f9401a11 	ldr	x17, [x16, #48]
  4006a8:	9100c210 	add	x16, x16, #0x30
  4006ac:	d61f0220 	br	x17

00000000004006b0 <abort@plt>:
  4006b0:	d0000090 	adrp	x16, 412000 <perror@GLIBC_2.17>
  4006b4:	f9401e11 	ldr	x17, [x16, #56]
  4006b8:	9100e210 	add	x16, x16, #0x38
  4006bc:	d61f0220 	br	x17

00000000004006c0 <read@plt>:
  4006c0:	d0000090 	adrp	x16, 412000 <perror@GLIBC_2.17>
  4006c4:	f9402211 	ldr	x17, [x16, #64]
  4006c8:	91010210 	add	x16, x16, #0x40
  4006cc:	d61f0220 	br	x17

00000000004006d0 <printf@plt>:
  4006d0:	d0000090 	adrp	x16, 412000 <perror@GLIBC_2.17>
  4006d4:	f9402611 	ldr	x17, [x16, #72]
  4006d8:	91012210 	add	x16, x16, #0x48
  4006dc:	d61f0220 	br	x17

Disassembly of section .text:

00000000004006e0 <_start>:
  4006e0:	d280001d 	mov	x29, #0x0                   	// #0
  4006e4:	d280001e 	mov	x30, #0x0                   	// #0
  4006e8:	aa0003e5 	mov	x5, x0
  4006ec:	f94003e1 	ldr	x1, [sp]
  4006f0:	910023e2 	add	x2, sp, #0x8
  4006f4:	910003e6 	mov	x6, sp
  4006f8:	580000c0 	ldr	x0, 400710 <_start+0x30>
  4006fc:	580000e3 	ldr	x3, 400718 <_start+0x38>
  400700:	58000104 	ldr	x4, 400720 <_start+0x40>
  400704:	97ffffdb 	bl	400670 <__libc_start_main@plt>
  400708:	97ffffea 	bl	4006b0 <abort@plt>
  40070c:	00000000 	.inst	0x00000000 ; undefined
  400710:	004007dc 	.word	0x004007dc
  400714:	00000000 	.word	0x00000000
  400718:	00400c80 	.word	0x00400c80
  40071c:	00000000 	.word	0x00000000
  400720:	00400d00 	.word	0x00400d00
  400724:	00000000 	.word	0x00000000

0000000000400728 <call_weak_fn>:
  400728:	b0000080 	adrp	x0, 411000 <__FRAME_END__+0x10084>
  40072c:	f947f000 	ldr	x0, [x0, #4064]
  400730:	b4000040 	cbz	x0, 400738 <call_weak_fn+0x10>
  400734:	17ffffd7 	b	400690 <__gmon_start__@plt>
  400738:	d65f03c0 	ret
  40073c:	00000000 	.inst	0x00000000 ; undefined

0000000000400740 <deregister_tm_clones>:
  400740:	d0000080 	adrp	x0, 412000 <perror@GLIBC_2.17>
  400744:	91018000 	add	x0, x0, #0x60
  400748:	d0000081 	adrp	x1, 412000 <perror@GLIBC_2.17>
  40074c:	91018021 	add	x1, x1, #0x60
  400750:	eb00003f 	cmp	x1, x0
  400754:	540000a0 	b.eq	400768 <deregister_tm_clones+0x28>  // b.none
  400758:	90000001 	adrp	x1, 400000 <_init-0x608>
  40075c:	f9469021 	ldr	x1, [x1, #3360]
  400760:	b4000041 	cbz	x1, 400768 <deregister_tm_clones+0x28>
  400764:	d61f0020 	br	x1
  400768:	d65f03c0 	ret
  40076c:	d503201f 	nop

0000000000400770 <register_tm_clones>:
  400770:	d0000080 	adrp	x0, 412000 <perror@GLIBC_2.17>
  400774:	91018000 	add	x0, x0, #0x60
  400778:	d0000081 	adrp	x1, 412000 <perror@GLIBC_2.17>
  40077c:	91018021 	add	x1, x1, #0x60
  400780:	cb000021 	sub	x1, x1, x0
  400784:	9343fc21 	asr	x1, x1, #3
  400788:	8b41fc21 	add	x1, x1, x1, lsr #63
  40078c:	9341fc21 	asr	x1, x1, #1
  400790:	b40000a1 	cbz	x1, 4007a4 <register_tm_clones+0x34>
  400794:	90000002 	adrp	x2, 400000 <_init-0x608>
  400798:	f9469442 	ldr	x2, [x2, #3368]
  40079c:	b4000042 	cbz	x2, 4007a4 <register_tm_clones+0x34>
  4007a0:	d61f0040 	br	x2
  4007a4:	d65f03c0 	ret

00000000004007a8 <__do_global_dtors_aux>:
  4007a8:	a9be7bfd 	stp	x29, x30, [sp, #-32]!
  4007ac:	910003fd 	mov	x29, sp
  4007b0:	f9000bf3 	str	x19, [sp, #16]
  4007b4:	d0000093 	adrp	x19, 412000 <perror@GLIBC_2.17>
  4007b8:	39418260 	ldrb	w0, [x19, #96]
  4007bc:	35000080 	cbnz	w0, 4007cc <__do_global_dtors_aux+0x24>
  4007c0:	97ffffe0 	bl	400740 <deregister_tm_clones>
  4007c4:	52800020 	mov	w0, #0x1                   	// #1
  4007c8:	39018260 	strb	w0, [x19, #96]
  4007cc:	f9400bf3 	ldr	x19, [sp, #16]
  4007d0:	a8c27bfd 	ldp	x29, x30, [sp], #32
  4007d4:	d65f03c0 	ret

00000000004007d8 <frame_dummy>:
  4007d8:	17ffffe6 	b	400770 <register_tm_clones>

00000000004007dc <main>:
  4007dc:	a9b27bfd 	stp	x29, x30, [sp, #-224]!
  4007e0:	910003fd 	mov	x29, sp
  4007e4:	a90153f3 	stp	x19, x20, [sp, #16]
  4007e8:	a9025bf5 	stp	x21, x22, [sp, #32]
  4007ec:	a90363f7 	stp	x23, x24, [sp, #48]
  4007f0:	a9046bf9 	stp	x25, x26, [sp, #64]
  4007f4:	f9002bfb 	str	x27, [sp, #80]
  4007f8:	b9006fa0 	str	w0, [x29, #108]
  4007fc:	f90033a1 	str	x1, [x29, #96]
  400800:	910003e0 	mov	x0, sp
  400804:	aa0003fb 	mov	x27, x0
  400808:	b9406fa0 	ldr	w0, [x29, #108]
  40080c:	7100101f 	cmp	w0, #0x4
  400810:	54000060 	b.eq	40081c <main+0x40>  // b.none
  400814:	12800000 	mov	w0, #0xffffffff            	// #-1
  400818:	14000110 	b	400c58 <main+0x47c>
  40081c:	f94033a0 	ldr	x0, [x29, #96]
  400820:	91002000 	add	x0, x0, #0x8
  400824:	f9400000 	ldr	x0, [x0]
  400828:	52800001 	mov	w1, #0x0                   	// #0
  40082c:	97ffff8d 	bl	400660 <open@plt>
  400830:	b900d7a0 	str	w0, [x29, #212]
  400834:	b940d7a0 	ldr	w0, [x29, #212]
  400838:	3100041f 	cmn	w0, #0x1
  40083c:	540000c1 	b.ne	400854 <main+0x78>  // b.any
  400840:	90000000 	adrp	x0, 400000 <_init-0x608>
  400844:	9134c000 	add	x0, x0, #0xd30
  400848:	97ffff7e 	bl	400640 <perror@plt>
  40084c:	12800020 	mov	w0, #0xfffffffe            	// #-2
  400850:	14000102 	b	400c58 <main+0x47c>
  400854:	f94033a0 	ldr	x0, [x29, #96]
  400858:	91004000 	add	x0, x0, #0x10
  40085c:	f9400000 	ldr	x0, [x0]
  400860:	52803fe2 	mov	w2, #0x1ff                 	// #511
  400864:	52804841 	mov	w1, #0x242                 	// #578
  400868:	97ffff7e 	bl	400660 <open@plt>
  40086c:	b900d3a0 	str	w0, [x29, #208]
  400870:	b940d3a0 	ldr	w0, [x29, #208]
  400874:	7100001f 	cmp	w0, #0x0
  400878:	540000ca 	b.ge	400890 <main+0xb4>  // b.tcont
  40087c:	90000000 	adrp	x0, 400000 <_init-0x608>
  400880:	91352000 	add	x0, x0, #0xd48
  400884:	97ffff6f 	bl	400640 <perror@plt>
  400888:	12800040 	mov	w0, #0xfffffffd            	// #-3
  40088c:	140000f3 	b	400c58 <main+0x47c>
  400890:	f94033a0 	ldr	x0, [x29, #96]
  400894:	91006000 	add	x0, x0, #0x18
  400898:	f9400000 	ldr	x0, [x0]
  40089c:	97ffff6d 	bl	400650 <atoi@plt>
  4008a0:	b900cfa0 	str	w0, [x29, #204]
  4008a4:	9101e3a0 	add	x0, x29, #0x78
  4008a8:	d28006c2 	mov	x2, #0x36                  	// #54
  4008ac:	aa0003e1 	mov	x1, x0
  4008b0:	b940d7a0 	ldr	w0, [x29, #212]
  4008b4:	97ffff83 	bl	4006c0 <read@plt>
  4008b8:	b900cba0 	str	w0, [x29, #200]
  4008bc:	3941e3a0 	ldrb	w0, [x29, #120]
  4008c0:	2a0003e1 	mov	w1, w0
  4008c4:	90000000 	adrp	x0, 400000 <_init-0x608>
  4008c8:	91358000 	add	x0, x0, #0xd60
  4008cc:	97ffff81 	bl	4006d0 <printf@plt>
  4008d0:	3941e7a0 	ldrb	w0, [x29, #121]
  4008d4:	2a0003e1 	mov	w1, w0
  4008d8:	90000000 	adrp	x0, 400000 <_init-0x608>
  4008dc:	91360000 	add	x0, x0, #0xd80
  4008e0:	97ffff7c 	bl	4006d0 <printf@plt>
  4008e4:	b847a3a1 	ldur	w1, [x29, #122]
  4008e8:	90000000 	adrp	x0, 400000 <_init-0x608>
  4008ec:	91368000 	add	x0, x0, #0xda0
  4008f0:	97ffff78 	bl	4006d0 <printf@plt>
  4008f4:	7940ffa0 	ldrh	w0, [x29, #126]
  4008f8:	2a0003e1 	mov	w1, w0
  4008fc:	90000000 	adrp	x0, 400000 <_init-0x608>
  400900:	91370000 	add	x0, x0, #0xdc0
  400904:	97ffff73 	bl	4006d0 <printf@plt>
  400908:	794103a0 	ldrh	w0, [x29, #128]
  40090c:	2a0003e1 	mov	w1, w0
  400910:	90000000 	adrp	x0, 400000 <_init-0x608>
  400914:	91378000 	add	x0, x0, #0xde0
  400918:	97ffff6e 	bl	4006d0 <printf@plt>
  40091c:	b84823a1 	ldur	w1, [x29, #130]
  400920:	90000000 	adrp	x0, 400000 <_init-0x608>
  400924:	91380000 	add	x0, x0, #0xe00
  400928:	97ffff6a 	bl	4006d0 <printf@plt>
  40092c:	b84863a1 	ldur	w1, [x29, #134]
  400930:	90000000 	adrp	x0, 400000 <_init-0x608>
  400934:	91388000 	add	x0, x0, #0xe20
  400938:	97ffff66 	bl	4006d0 <printf@plt>
  40093c:	b848a3a1 	ldur	w1, [x29, #138]
  400940:	90000000 	adrp	x0, 400000 <_init-0x608>
  400944:	91390000 	add	x0, x0, #0xe40
  400948:	97ffff62 	bl	4006d0 <printf@plt>
  40094c:	b848e3a1 	ldur	w1, [x29, #142]
  400950:	90000000 	adrp	x0, 400000 <_init-0x608>
  400954:	91398000 	add	x0, x0, #0xe60
  400958:	97ffff5e 	bl	4006d0 <printf@plt>
  40095c:	794127a0 	ldrh	w0, [x29, #146]
  400960:	2a0003e1 	mov	w1, w0
  400964:	90000000 	adrp	x0, 400000 <_init-0x608>
  400968:	913a0000 	add	x0, x0, #0xe80
  40096c:	97ffff59 	bl	4006d0 <printf@plt>
  400970:	79412ba0 	ldrh	w0, [x29, #148]
  400974:	2a0003e1 	mov	w1, w0
  400978:	90000000 	adrp	x0, 400000 <_init-0x608>
  40097c:	913a8000 	add	x0, x0, #0xea0
  400980:	97ffff54 	bl	4006d0 <printf@plt>
  400984:	b84963a1 	ldur	w1, [x29, #150]
  400988:	90000000 	adrp	x0, 400000 <_init-0x608>
  40098c:	913b0000 	add	x0, x0, #0xec0
  400990:	97ffff50 	bl	4006d0 <printf@plt>
  400994:	b849a3a1 	ldur	w1, [x29, #154]
  400998:	90000000 	adrp	x0, 400000 <_init-0x608>
  40099c:	913b8000 	add	x0, x0, #0xee0
  4009a0:	97ffff4c 	bl	4006d0 <printf@plt>
  4009a4:	b849e3a1 	ldur	w1, [x29, #158]
  4009a8:	90000000 	adrp	x0, 400000 <_init-0x608>
  4009ac:	913c0000 	add	x0, x0, #0xf00
  4009b0:	97ffff48 	bl	4006d0 <printf@plt>
  4009b4:	b84a23a1 	ldur	w1, [x29, #162]
  4009b8:	90000000 	adrp	x0, 400000 <_init-0x608>
  4009bc:	913c8000 	add	x0, x0, #0xf20
  4009c0:	97ffff44 	bl	4006d0 <printf@plt>
  4009c4:	b84a63a1 	ldur	w1, [x29, #166]
  4009c8:	90000000 	adrp	x0, 400000 <_init-0x608>
  4009cc:	913d0000 	add	x0, x0, #0xf40
  4009d0:	97ffff40 	bl	4006d0 <printf@plt>
  4009d4:	b84aa3a1 	ldur	w1, [x29, #170]
  4009d8:	90000000 	adrp	x0, 400000 <_init-0x608>
  4009dc:	913d8000 	add	x0, x0, #0xf60
  4009e0:	97ffff3c 	bl	4006d0 <printf@plt>
  4009e4:	b849a3a0 	ldur	w0, [x29, #154]
  4009e8:	2a0003e1 	mov	w1, w0
  4009ec:	d1000421 	sub	x1, x1, #0x1
  4009f0:	f90063a1 	str	x1, [x29, #192]
  4009f4:	2a0003e1 	mov	w1, w0
  4009f8:	aa0103f9 	mov	x25, x1
  4009fc:	d280001a 	mov	x26, #0x0                   	// #0
  400a00:	d37dff21 	lsr	x1, x25, #61
  400a04:	d37df356 	lsl	x22, x26, #3
  400a08:	aa160036 	orr	x22, x1, x22
  400a0c:	d37df335 	lsl	x21, x25, #3
  400a10:	2a0003e1 	mov	w1, w0
  400a14:	aa0103f7 	mov	x23, x1
  400a18:	d2800018 	mov	x24, #0x0                   	// #0
  400a1c:	d37dfee1 	lsr	x1, x23, #61
  400a20:	d37df314 	lsl	x20, x24, #3
  400a24:	aa140034 	orr	x20, x1, x20
  400a28:	d37df2f3 	lsl	x19, x23, #3
  400a2c:	2a0003e0 	mov	w0, w0
  400a30:	91003c00 	add	x0, x0, #0xf
  400a34:	d344fc00 	lsr	x0, x0, #4
  400a38:	d37cec00 	lsl	x0, x0, #4
  400a3c:	cb2063ff 	sub	sp, sp, x0
  400a40:	910003e0 	mov	x0, sp
  400a44:	91000000 	add	x0, x0, #0x0
  400a48:	f9005fa0 	str	x0, [x29, #184]
  400a4c:	f9405fa0 	ldr	x0, [x29, #184]
  400a50:	b849a3a1 	ldur	w1, [x29, #154]
  400a54:	2a0103e1 	mov	w1, w1
  400a58:	aa0103e2 	mov	x2, x1
  400a5c:	aa0003e1 	mov	x1, x0
  400a60:	b940d7a0 	ldr	w0, [x29, #212]
  400a64:	97ffff17 	bl	4006c0 <read@plt>
  400a68:	b940d7a0 	ldr	w0, [x29, #212]
  400a6c:	97ffff05 	bl	400680 <close@plt>
  400a70:	9101e3a0 	add	x0, x29, #0x78
  400a74:	d28006c2 	mov	x2, #0x36                  	// #54
  400a78:	aa0003e1 	mov	x1, x0
  400a7c:	b940d3a0 	ldr	w0, [x29, #208]
  400a80:	97ffff08 	bl	4006a0 <write@plt>
  400a84:	f9005bbf 	str	xzr, [x29, #176]
  400a88:	b900dbbf 	str	wzr, [x29, #216]
  400a8c:	14000023 	b	400b18 <main+0x33c>
  400a90:	b900dfbf 	str	wzr, [x29, #220]
  400a94:	1400001b 	b	400b00 <main+0x324>
  400a98:	f9405fa2 	ldr	x2, [x29, #184]
  400a9c:	b940dba1 	ldr	w1, [x29, #216]
  400aa0:	52806400 	mov	w0, #0x320                 	// #800
  400aa4:	1b007c21 	mul	w1, w1, w0
  400aa8:	b940dfa0 	ldr	w0, [x29, #220]
  400aac:	0b000021 	add	w1, w1, w0
  400ab0:	2a0103e0 	mov	w0, w1
  400ab4:	531f7800 	lsl	w0, w0, #1
  400ab8:	0b010000 	add	w0, w0, w1
  400abc:	93407c00 	sxtw	x0, w0
  400ac0:	8b000040 	add	x0, x2, x0
  400ac4:	f9005ba0 	str	x0, [x29, #176]
  400ac8:	f9405ba0 	ldr	x0, [x29, #176]
  400acc:	12800001 	mov	w1, #0xffffffff            	// #-1
  400ad0:	39000001 	strb	w1, [x0]
  400ad4:	f9405ba0 	ldr	x0, [x29, #176]
  400ad8:	91000400 	add	x0, x0, #0x1
  400adc:	12800001 	mov	w1, #0xffffffff            	// #-1
  400ae0:	39000001 	strb	w1, [x0]
  400ae4:	f9405ba0 	ldr	x0, [x29, #176]
  400ae8:	91000800 	add	x0, x0, #0x2
  400aec:	12800001 	mov	w1, #0xffffffff            	// #-1
  400af0:	39000001 	strb	w1, [x0]
  400af4:	b940dfa0 	ldr	w0, [x29, #220]
  400af8:	11000400 	add	w0, w0, #0x1
  400afc:	b900dfa0 	str	w0, [x29, #220]
  400b00:	b940dfa0 	ldr	w0, [x29, #220]
  400b04:	7100241f 	cmp	w0, #0x9
  400b08:	54fffc8d 	b.le	400a98 <main+0x2bc>
  400b0c:	b940dba0 	ldr	w0, [x29, #216]
  400b10:	11000400 	add	w0, w0, #0x1
  400b14:	b900dba0 	str	w0, [x29, #216]
  400b18:	b940dba0 	ldr	w0, [x29, #216]
  400b1c:	7100241f 	cmp	w0, #0x9
  400b20:	54fffb8d 	b.le	400a90 <main+0x2b4>
  400b24:	b900dbbf 	str	wzr, [x29, #216]
  400b28:	14000046 	b	400c40 <main+0x464>
  400b2c:	b900dfbf 	str	wzr, [x29, #220]
  400b30:	1400003e 	b	400c28 <main+0x44c>
  400b34:	f9405fa2 	ldr	x2, [x29, #184]
  400b38:	b940dba1 	ldr	w1, [x29, #216]
  400b3c:	52806400 	mov	w0, #0x320                 	// #800
  400b40:	1b007c21 	mul	w1, w1, w0
  400b44:	b940dfa0 	ldr	w0, [x29, #220]
  400b48:	0b000021 	add	w1, w1, w0
  400b4c:	2a0103e0 	mov	w0, w1
  400b50:	531f7800 	lsl	w0, w0, #1
  400b54:	0b010000 	add	w0, w0, w1
  400b58:	93407c00 	sxtw	x0, w0
  400b5c:	8b000040 	add	x0, x2, x0
  400b60:	f9005ba0 	str	x0, [x29, #176]
  400b64:	f9405ba0 	ldr	x0, [x29, #176]
  400b68:	91000800 	add	x0, x0, #0x2
  400b6c:	39400000 	ldrb	w0, [x0]
  400b70:	2a0003e1 	mov	w1, w0
  400b74:	f9405ba0 	ldr	x0, [x29, #176]
  400b78:	91000400 	add	x0, x0, #0x1
  400b7c:	39400000 	ldrb	w0, [x0]
  400b80:	0b000020 	add	w0, w1, w0
  400b84:	f9405ba1 	ldr	x1, [x29, #176]
  400b88:	39400021 	ldrb	w1, [x1]
  400b8c:	0b010000 	add	w0, w0, w1
  400b90:	528aaac1 	mov	w1, #0x5556                	// #21846
  400b94:	72aaaaa1 	movk	w1, #0x5555, lsl #16
  400b98:	9b217c01 	smull	x1, w0, w1
  400b9c:	d360fc21 	lsr	x1, x1, #32
  400ba0:	131f7c00 	asr	w0, w0, #31
  400ba4:	4b000020 	sub	w0, w1, w0
  400ba8:	3902bfa0 	strb	w0, [x29, #175]
  400bac:	3942bfa0 	ldrb	w0, [x29, #175]
  400bb0:	b940cfa1 	ldr	w1, [x29, #204]
  400bb4:	6b00003f 	cmp	w1, w0
  400bb8:	5400014d 	b.le	400be0 <main+0x404>
  400bbc:	f9405ba0 	ldr	x0, [x29, #176]
  400bc0:	3900001f 	strb	wzr, [x0]
  400bc4:	f9405ba0 	ldr	x0, [x29, #176]
  400bc8:	91000400 	add	x0, x0, #0x1
  400bcc:	3900001f 	strb	wzr, [x0]
  400bd0:	f9405ba0 	ldr	x0, [x29, #176]
  400bd4:	91000800 	add	x0, x0, #0x2
  400bd8:	3900001f 	strb	wzr, [x0]
  400bdc:	1400000c 	b	400c0c <main+0x430>
  400be0:	f9405ba0 	ldr	x0, [x29, #176]
  400be4:	3942bfa1 	ldrb	w1, [x29, #175]
  400be8:	39000001 	strb	w1, [x0]
  400bec:	f9405ba0 	ldr	x0, [x29, #176]
  400bf0:	91000400 	add	x0, x0, #0x1
  400bf4:	3942bfa1 	ldrb	w1, [x29, #175]
  400bf8:	39000001 	strb	w1, [x0]
  400bfc:	f9405ba0 	ldr	x0, [x29, #176]
  400c00:	91000800 	add	x0, x0, #0x2
  400c04:	3942bfa1 	ldrb	w1, [x29, #175]
  400c08:	39000001 	strb	w1, [x0]
  400c0c:	d2800062 	mov	x2, #0x3                   	// #3
  400c10:	f9405ba1 	ldr	x1, [x29, #176]
  400c14:	b940d3a0 	ldr	w0, [x29, #208]
  400c18:	97fffea2 	bl	4006a0 <write@plt>
  400c1c:	b940dfa0 	ldr	w0, [x29, #220]
  400c20:	11000400 	add	w0, w0, #0x1
  400c24:	b900dfa0 	str	w0, [x29, #220]
  400c28:	b940dfa0 	ldr	w0, [x29, #220]
  400c2c:	710c7c1f 	cmp	w0, #0x31f
  400c30:	54fff82d 	b.le	400b34 <main+0x358>
  400c34:	b940dba0 	ldr	w0, [x29, #216]
  400c38:	11000400 	add	w0, w0, #0x1
  400c3c:	b900dba0 	str	w0, [x29, #216]
  400c40:	b940dba0 	ldr	w0, [x29, #216]
  400c44:	71077c1f 	cmp	w0, #0x1df
  400c48:	54fff72d 	b.le	400b2c <main+0x350>
  400c4c:	b940d3a0 	ldr	w0, [x29, #208]
  400c50:	97fffe8c 	bl	400680 <close@plt>
  400c54:	52800000 	mov	w0, #0x0                   	// #0
  400c58:	9100037f 	mov	sp, x27
  400c5c:	910003bf 	mov	sp, x29
  400c60:	a94153f3 	ldp	x19, x20, [sp, #16]
  400c64:	a9425bf5 	ldp	x21, x22, [sp, #32]
  400c68:	a94363f7 	ldp	x23, x24, [sp, #48]
  400c6c:	a9446bf9 	ldp	x25, x26, [sp, #64]
  400c70:	f9402bfb 	ldr	x27, [sp, #80]
  400c74:	a8ce7bfd 	ldp	x29, x30, [sp], #224
  400c78:	d65f03c0 	ret
  400c7c:	00000000 	.inst	0x00000000 ; undefined

0000000000400c80 <__libc_csu_init>:
  400c80:	a9bc7bfd 	stp	x29, x30, [sp, #-64]!
  400c84:	910003fd 	mov	x29, sp
  400c88:	a901d7f4 	stp	x20, x21, [sp, #24]
  400c8c:	b0000094 	adrp	x20, 411000 <__FRAME_END__+0x10084>
  400c90:	b0000095 	adrp	x21, 411000 <__FRAME_END__+0x10084>
  400c94:	91374294 	add	x20, x20, #0xdd0
  400c98:	913722b5 	add	x21, x21, #0xdc8
  400c9c:	a902dff6 	stp	x22, x23, [sp, #40]
  400ca0:	cb150294 	sub	x20, x20, x21
  400ca4:	f9001ff8 	str	x24, [sp, #56]
  400ca8:	2a0003f6 	mov	w22, w0
  400cac:	aa0103f7 	mov	x23, x1
  400cb0:	9343fe94 	asr	x20, x20, #3
  400cb4:	aa0203f8 	mov	x24, x2
  400cb8:	97fffe54 	bl	400608 <_init>
  400cbc:	b4000194 	cbz	x20, 400cec <__libc_csu_init+0x6c>
  400cc0:	f9000bb3 	str	x19, [x29, #16]
  400cc4:	d2800013 	mov	x19, #0x0                   	// #0
  400cc8:	f8737aa3 	ldr	x3, [x21, x19, lsl #3]
  400ccc:	aa1803e2 	mov	x2, x24
  400cd0:	aa1703e1 	mov	x1, x23
  400cd4:	2a1603e0 	mov	w0, w22
  400cd8:	91000673 	add	x19, x19, #0x1
  400cdc:	d63f0060 	blr	x3
  400ce0:	eb13029f 	cmp	x20, x19
  400ce4:	54ffff21 	b.ne	400cc8 <__libc_csu_init+0x48>  // b.any
  400ce8:	f9400bb3 	ldr	x19, [x29, #16]
  400cec:	a941d7f4 	ldp	x20, x21, [sp, #24]
  400cf0:	a942dff6 	ldp	x22, x23, [sp, #40]
  400cf4:	f9401ff8 	ldr	x24, [sp, #56]
  400cf8:	a8c47bfd 	ldp	x29, x30, [sp], #64
  400cfc:	d65f03c0 	ret

0000000000400d00 <__libc_csu_fini>:
  400d00:	d65f03c0 	ret

Disassembly of section .fini:

0000000000400d04 <_fini>:
  400d04:	a9bf7bfd 	stp	x29, x30, [sp, #-16]!
  400d08:	910003fd 	mov	x29, sp
  400d0c:	a8c17bfd 	ldp	x29, x30, [sp], #16
  400d10:	d65f03c0 	ret
